1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method which forms an isolation region with a narrow isolation width on a semiconductor substrate without leaving voids, surface dents or the like. In addition, the present invention relates to a method for simultaneously forming an isolation region with a narrow isolation width and an isolation region with a wide isolation width.
2. Description of the Related Art
When forming a switching element such as a transistor on a semiconductor substrate in a semiconductor device such as a dynamic random access memory (DRAM), an isolation region is formed and a transistor region (active region) is defined in the semiconductor substrate. In recent semiconductor devices, shallow trench isolation (STI) is generally performed to form an isolation region and fill a trench formed in a semiconductor substrate with an insulating material.
A filling method in the STI for manufacture of semiconductor devices tends to be restricted by a high aspect ratio caused by miniaturization, and defective fill (voids) may occur in conventional high-density plasma chemical vapor deposition (HDP-CVD) techniques in forming an isolation region having an isolation width of 100 nm or below by STI.
To overcome such a problem, a method which employs a spin-on-dielectric (SOD) film has been proposed as a method for filling, in a void-free manner, a trench formed by STI. However, the SOD film uses a solvent, which may cause environmental harm. Moreover, impurities derived from the applied solvent may remain in the formed film, which may affect on characteristics of semiconductor elements. Therefore, a flowable CVD method has been proposed to replace the method employing the SOD film. The filling process in the flowable CVD method uses organosilane or organosiloxane as a raw material, forms a flowable silicon compound (mostly, silanol (Si(OH)4)) film by the CVD method, and converts the film to a silicon oxide film by an oxidation reaction. The flowable silicon compound film may sink into a narrow space, thereby improving gap-fill performance and leaving no voids (U.S. Pat. No. 7,582,555).
However, in the filling process by the flowable CVD method, although not so serious as those in the SOD film, film shrinkage may occur during conversion into the oxide film, and therefore, the oxide film in the isolation region formed by STI and having a narrower isolation width tends to be more porous. The less dense oxide film has a high wet etching rate, which may easily cause to defects in processing.
To solve the above-enumerated problems, a shallow trench isolation process in which a flowable CVD method and an HDP-CVD method are combined has been proposed by Sung-Woong Chung et al., (“Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRM”, Electron Devices Meeting, 2002, IEDM'02, Digest. International, p. 233 to 236). Chung et al. have proposed a stacked structure in that an oxide film formed by a flowable CVD method which enables excellent filling is used as bottom-up fill, and an oxide film formed by an HDP-CVD method which provides superior film quality is stacked on the oxide film formed by the flowable CVD method.
The present inventors have recognized that, in the aforementioned stacked structure, it is significant to control the height of the bottom-up fill oxide film in a memory cell region. If the height of the bottom-up fill oxide film is low, the oxide film formed by an HDP-CVD method may have defective fill (voids).
Furthermore, the present inventors have recognized that silicon oxide films formed by conventional flowable CVD methods tend to be porous, which may lead to a high wet etching rate. For example, wide isolation regions are formed together with narrow isolation regions in a semiconductor device such as a DRAM, however, silicon oxide films formed by a flowable CVD method may suffer from problems of different heights of bottom-up fill oxide films caused by isolation widths. When wet etching is performed in the final step of a process for forming an isolation region, the etching rapidly progresses when a silicon oxide film is obtained by a flowable CVD method with a high wet etching rate from the oxide film formed by an HDP-CVD method with a low wet etching rate, which may result in non-uniform heights of surfaces of isolation regions.